library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.faw_types.all;

entity TestingUnit is
        port(   
                        clk_tu : in  std_logic;
                        reset_tu : in STD_LOGIC;
           pixel_merged_tu : in  std_logic_vector (23 downto 0);
           frame_valid_tu : inout  std_logic;
           line_valid_tu : inout  std_logic;
           pixel_valid_tu : inout  std_logic;
           left_out_tu : inout  STD_LOGIC_VECTOR (7 downto 0);
           right_out_tu : inout  STD_LOGIC_VECTOR (7 downto 0);
                          i_tu : inout COUNTER_ROWS;
                          j_tu : inout COUNTER_COLUMNS;
                        counter_cc_ref_tu : out  COUNTER_CENTRALS;
         enable_cc_ref_tu : out  STD_LOGIC;
                        dina_tu : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                        addra_tu : INOUT STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
                        enb_tu : inout STD_LOGIC;
                        addrb_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
                        doutb_tu : out std_logic_vector(7 downto 0);
                        pixels_centrali_target_tu : out TCPSR_SR_DATA_BUS;
                        
                        --solo per test
                        br_sr_bus_tu : inout std_logic_vector(7 downto 0); 
                        addrb_tcpc_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
                        addra_tcpc_tu : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
--                      en_rspsrc_tu :  inout SR_ENABLE_BUS;
                        we_rspsrc_tu : inout SR_ENABLE_ROWS;
                        we_tspsrc_tu : inout TARGET_SR_ENABLE_ROWS;
                        data_out_tspsrc_tu: inout TSPSRC_SR_DATA_BUS;
                        data_out_rspsrc_tu: inout RSPSRC_SR_DATA_BUS
                        );
end TestingUnit;

architecture Archi of TestingUnit is

        component Counters is
                                Port ( clk_c : in  STD_LOGIC;
                                reset_c : in STD_LOGIC;
           pixel_valid_c : in  STD_LOGIC;
           line_valid_c : in  STD_LOGIC;
                          frame_valid_c : in STD_LOGIC;
                          i_c : out COUNTER_ROWS;
                          j_c : out COUNTER_COLUMNS);
        end component;

        
        component Source is
                        Port ( clk_s : in  std_logic;
           pixel_merged_s : in  std_logic_vector (23 downto 0);  
           frame_valid_s : out  std_logic;
           line_valid_s : out  std_logic;
           pixel_valid_s : out  std_logic;
           left_out_s : out  STD_LOGIC_VECTOR (7 downto 0);
           right_out_s : out  STD_LOGIC_VECTOR (7 downto 0)
                                );
        end component;
        
        component BR_CENTRALI_REFERENCE
                PORT (
                        clka : IN STD_LOGIC;
                        ena : IN STD_LOGIC;
                        wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
                        addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
                        dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        clkb : IN STD_LOGIC;
                        enb : IN STD_LOGIC;
                        rstb : IN STD_LOGIC;
                        addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
                        doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                );
        end component;
        
        component RefCentralPointsController
                Port(
                        i_rcpc : in  COUNTER_ROWS;
         j_rcpc : in  COUNTER_COLUMNS;
                        clk_rcpc : in STD_LOGIC;
                        reset_rcpc: in STD_LOGIC;
         pixel_valid_rcpc : in  STD_LOGIC;
         line_valid_rcpc : in  STD_LOGIC;
                        frame_valid_rcpc : in STD_LOGIC;
         pixel_reference_rcpc : in  STD_LOGIC_VECTOR (7 downto 0);
         counter_cc_ref_rcpc : out  COUNTER_CENTRALS;
         enable_cc_ref_rcpc : out  STD_LOGIC;
         ena_rcpc : out  STD_LOGIC;
         wea_rcpc : out  STD_LOGIC_VECTOR (0 downto 0);
         addra_rcpc : out  STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
         dina_rcpc : out  STD_LOGIC_VECTOR (7 downto 0);
                        enb_rcpc : out STD_LOGIC;
                        addrb_rcpc : out STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0)
                );
        end component;
        
        component RefSampledPointsSRController
                Port(
                          clk_rspsrc : in  STD_LOGIC;
                          reset_rspsrc : in STD_LOGIC;
           i_rspsrc : in  COUNTER_ROWS;
           j_rspsrc : in  COUNTER_COLUMNS;
                          we_rspsrc : out SR_ENABLE_ROWS;
       --    en_rspsrc : in   SR_ENABLE_BUS; -- la macchina a stati setta questi bit
       --    sset_rspsrc : in  STD_LOGIC;
           sclear_rspsrc : out  STD_LOGIC
                --        en_rows_rspsrc : in SR_ENABLE_ROWS; -- la macchina a stati setta questi bit
                --        data_out_rspsrc : out  RSPSRC_SR_DATA_BUS
                );
        end component;
        
        component RefSampledPointsShiftRegisterS is
    Port ( clk_rspsrs : in  STD_LOGIC;
           data_in_rspsrs : in  STD_LOGIC_VECTOR (7 downto 0);
           we_rspsrs : in  SR_ENABLE_ROWS;
           oe_rspsrs : in  SR_ENABLE_BUS;
                          oe_rspsrs_rows : in SR_ENABLE_ROWS;
           sclear_rspsrs : in  STD_LOGIC;
           data_out_rspsrs : out  RSPSRC_SR_DATA_BUS);
        end component;
        
        component SampledPointsEnabler is
    Port ( i_spe : in  COUNTER_ROWS;
           j_spe : in  COUNTER_COLUMNS;
           clk_spe : in  STD_LOGIC;
                          reset_spe : in STD_LOGIC;
           en_spe : out  SR_ENABLE_BUS;
           en_rows_spe : out  SR_ENABLE_ROWS);
        end component;
        
        component TargetCentralPointsController is
        Port (    
                     frame_valid_tcpc : in STD_LOGIC;
                          line_valid_tcpc: in STD_LOGIC;
                          pixel_valid_tcpc : in STD_LOGIC;
                          i_tcpc : in  COUNTER_ROWS;
           j_tcpc : in  COUNTER_COLUMNS;
                          clk_tcpc : in STD_LOGIC;
                          reset_tcpc : in STD_LOGIC;
           pixel_taget_tcpc : in  STD_LOGIC_VECTOR (7 downto 0);
                          pixels_centrali_target_tcpc : out TCPSR_SR_DATA_BUS;
                          --solo per test
                          br_sr_bus : inout std_logic_vector(7 downto 0); 
                          addrb_tcpc : inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0);
                          addra_tcpc :  inout STD_LOGIC_VECTOR(N_BIT_BR_CENTRALS-1 DOWNTO 0)
           );
        end component;
        
        component TargetSampledPointsSRController
                Port(
                          clk_tspsrc : in  STD_LOGIC;
                          reset_tspsrc : in STD_LOGIC;
        --                camera_pixel_rspsrc : in  STD_LOGIC_VECTOR (7 downto 0);
           i_tspsrc : in  COUNTER_ROWS;
           j_tspsrc : in  COUNTER_COLUMNS;
                          we_tspsrc : out TARGET_SR_ENABLE_ROWS;
       --    en_rspsrc : in   SR_ENABLE_BUS; -- la macchina a stati setta questi bit
       --    sset_rspsrc : in  STD_LOGIC;
           sclear_tspsrc : out  STD_LOGIC
                --        en_rows_rspsrc : in SR_ENABLE_ROWS; -- la macchina a stati setta questi bit
                --        data_out_rspsrc : out  RSPSRC_SR_DATA_BUS
                );
        end component;
        
        component TargetSampledPointsShiftRegisterS is
    Port ( clk_tspsrs : in  STD_LOGIC;
           data_in_tspsrs : in  STD_LOGIC_VECTOR (7 downto 0);
           we_tspsrs : in  TARGET_SR_ENABLE_ROWS;
           oe_tspsrs : in  TARGET_SR_ENABLE_BUS;
           sclear_tspsrs : in  STD_LOGIC;
                          oe_tspsrs_rows : in TARGET_SR_ENABLE_ROWS;
           data_out_tspsrs : out  TSPSRC_SR_DATA_BUS);
        end component;
        
        component TargetSampledPointsEnabler is
    Port ( i_tspe : in  COUNTER_ROWS;
           j_tspe : in  COUNTER_COLUMNS;
           clk_tspe : in  STD_LOGIC;
                          reset_tspe : in STD_LOGIC;
           en_tspe : out  TARGET_SR_ENABLE_BUS;
           en_rows_tspe : out  TARGET_SR_ENABLE_ROWS);
        end component;
        
        signal clk_cg : std_logic;
        signal ena_test : std_logic;
        signal wea_test : std_logic_vector (0 downto 0);
        signal addra_test :  STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
   signal dina_test :  STD_LOGIC_VECTOR (7 downto 0);
        signal enb_test : std_logic;
        signal addrb_test :  STD_LOGIC_VECTOR (N_BIT_BR_CENTRALS-1 downto 0);
--      signal en_rspsrc_test :SR_ENABLE_BUS;
--  signal doutb_test :  STD_LOGIC_VECTOR (7 downto 0);
--      signal clk_test : std_logic;
--      signal pixel_valid_test : std_logic;
--      signal line_valid_test : std_logic;
--      signal frame_valid_test : std_logic;
   
   signal sclear_rspsrc_test:STD_LOGIC;
        signal en_rows_rspsrc_test : SR_ENABLE_ROWS;
   signal oe_rspsrs_test : SR_ENABLE_BUS;
--      signal we_rspsrc_test : SR_ENABLE_ROWS;
--segnali per target
   signal sclear_tspsrc_test:STD_LOGIC;
        signal en_rows_tspsrc_test : TARGET_SR_ENABLE_ROWS;
        signal we_tspsrc_test : TARGET_SR_ENABLE_ROWS;
   signal oe_tspsrs_test : TARGET_SR_ENABLE_BUS;
        

begin

        Counters_1 : Counters
                        port map(
                                clk_c =>clk_tu,
                                reset_c=>reset_tu,
                                pixel_valid_c=>pixel_valid_tu,
                                line_valid_c=>line_valid_tu,
                                frame_valid_c=>frame_valid_tu,
                                i_c=>i_tu,
                                j_c=>j_tu
                        );
        
                        
        Source_1 : Source
                        port map(
                                clk_s=>clk_tu,
                                pixel_valid_s=>pixel_valid_tu,
                                line_valid_s=>line_valid_tu,
                                frame_valid_s=>frame_valid_tu,
                                pixel_merged_s=>pixel_merged_tu,  
                                left_out_s => left_out_tu,
           right_out_s => right_out_tu
--                        counterCol_s=> counterCol_tu,
--                        counterRow_s=> counterRow_tu
                        );
                
        BR_CENTRALI_REFERENCE_1 : BR_CENTRALI_REFERENCE
                port map(
                        clka => clk_tu,
                        ena => ena_test,
                        wea => wea_test,
                        addra => addra_tu,
                        dina => dina_tu,
                        clkb => clk_tu,
                        enb => enb_tu,
                        rstb=>reset_tu,
                        addrb => addrb_tu,
                        doutb => doutb_tu
                );
                
        RefCentralPointsController_1 : RefCentralPointsController
                port map(
                        i_rcpc =>i_tu,
         j_rcpc =>j_tu,
                        clk_rcpc =>clk_tu,
                        reset_rcpc=>reset_tu,
         pixel_valid_rcpc =>pixel_valid_tu,
                        line_valid_rcpc=>line_valid_tu,
                        frame_valid_rcpc=>frame_valid_tu,
         pixel_reference_rcpc =>left_out_tu,
         counter_cc_ref_rcpc =>counter_cc_ref_tu,
         enable_cc_ref_rcpc =>enable_cc_ref_tu,
         ena_rcpc =>ena_test,
         wea_rcpc =>wea_test,
         addra_rcpc => addra_tu,
         dina_rcpc =>dina_tu,
                        enb_rcpc => enb_tu,
                        addrb_rcpc => addrb_tu
                );
                
                RefSampledPointsSRController_1 : RefSampledPointsSRController
                        port map(
                         clk_rspsrc =>clk_tu,
                         reset_rspsrc=>reset_tu,
                --  camera_pixel_rspsrc => left_out_tu,
--           br_pixel_rspsrc => data_out_rspbr_tu,
           i_rspsrc => i_tu,
           j_rspsrc => j_tu,
           we_rspsrc => we_rspsrc_tu,
     --      en_rspsrc => en_rspsrc_test,
           sclear_rspsrc =>sclear_rspsrc_test
        --                en_rows_rspsrc => en_rows_rspsrc_test,
                --        data_out_rspsrc => data_out_rspsrc_tu                 
                );
                
                RefSampledPointsShiftRegisterS_1 : RefSampledPointsShiftRegisterS
                        port map ( 
                                clk_rspsrs =>clk_tu,
           data_in_rspsrs => left_out_tu,
           we_rspsrs => we_rspsrc_tu,
           oe_rspsrs =>oe_rspsrs_test,
                          oe_rspsrs_rows =>en_rows_rspsrc_test,
           sclear_rspsrs =>sclear_rspsrc_test,
           data_out_rspsrs => data_out_rspsrc_tu
                          );
                
                SampledPointsEnabler_1 : SampledPointsEnabler 
                        port map ( 
                          i_spe => i_tu,
           j_spe => j_tu,
           clk_spe => clk_tu,
                          reset_spe=>reset_tu,
           en_spe => oe_rspsrs_test,
           en_rows_spe => en_rows_rspsrc_test
                );
                
                TargetCentralPointsController_1 :TargetCentralPointsController
                        port map(
                          frame_valid_tcpc=>frame_valid_tu,
                          line_valid_tcpc=> line_valid_tu,
                          pixel_valid_tcpc=>pixel_valid_tu,
                          i_tcpc=>i_tu,
									j_tcpc=>j_tu,
                          clk_tcpc=>clk_tu,
                          reset_tcpc=>reset_tu,
									pixel_taget_tcpc=>right_out_tu,
                          pixels_centrali_target_tcpc=>pixels_centrali_target_tu,
                          --solo peer tesrt
                          br_sr_bus=>br_sr_bus_tu, 
                          addrb_tcpc=>addrb_tcpc_tu,
                          addra_tcpc=>addra_tcpc_tu                       
                );
                
                TargetSampledPointsSRController_1 : TargetSampledPointsSRController
                        port map(
                         clk_tspsrc =>clk_tu,
                         reset_tspsrc=>reset_tu,
           i_tspsrc => i_tu,
           j_tspsrc => j_tu,
           we_tspsrc => we_tspsrc_tu,
           sclear_tspsrc =>sclear_tspsrc_test                   
                );
                
                TargetSampledPointsShiftRegisterS_1 : TargetSampledPointsShiftRegisterS
                        port map ( 
                                clk_tspsrs =>clk_tu,
           data_in_tspsrs => right_out_tu,
           we_tspsrs => we_tspsrc_tu,
           oe_tspsrs =>oe_tspsrs_test,
                          oe_tspsrs_rows=>en_rows_tspsrc_test,
           sclear_tspsrs =>sclear_tspsrc_test,
           data_out_tspsrs => data_out_tspsrc_tu
                          );
                          
                TargetSampledPointsEnabler_1 : TargetSampledPointsEnabler 
                        port map ( 
                          i_tspe => i_tu,
           j_tspe => j_tu,
           clk_tspe => clk_tu,
                          reset_tspe=>reset_tu,
           en_tspe => oe_tspsrs_test,
           en_rows_tspe => en_rows_tspsrc_test
                );
                
end Archi;